Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFET) has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits. One way to improve transistor performance is through selective application of stress to the transistor channel region. Stress distorts (i. e., strains) the semiconductor crystal lattice, and the distortion, in turn, affects the band alignment and charge transport properties of the semiconductor. By controlling the magnitude and distribution of stress in a finished device, manufacturers can increase carrier mobility and improve device performance. There are several existing approaches of introducing stress in the transistor channel region.
One conventional approach includes forming an epitaxial, strained silicon layer on a relaxed silicon germanium (SiGe) layer. Since the SiGe lattice is larger than Si, the SiGe layer stretches the epi-layer the lateral direction, i.e., the silicon will be under a biaxial tensile stress. Another approach includes growing an epitaxial layer of SiGe within recesses in the source/drain regions. In this case, lattice mismatch creates a uni-axial compressive stress within the channel region.
In still another approach, stress in the channel is introduced after the transistor is formed. In this approach, a high-stress film, such as silicon nitride, is formed over a completed transistor. In this case, the stressor, i.e., the film, is placed above the completed transistor structure. Frequently, the stressor is a tensile layer, which because of the geometry of the structure, induces a uni-axial tensile stress in the channel.
One problem facing CMOS manufacturing is that NMOS and PMOS devices require different types of stress in order to achieve increased carrier mobility. For example, a biaxial, tensile stress from a silicon nitride film increases NMOS performance approximately twofold. However, for a PMOS device, such a stress yields almost no improvement. With a PMOS device, a tensile stress improves performance when it is perpendicular to the channel, but it has nearly the opposite effect when it is parallel to the channel. Therefore, when a biaxial, tensile film is applied to a PMOS device, the two stress effects almost cancel each other out.
Workers in the art are aware of these problems. Therefore, new CMOS manufacturing techniques selectively address PMOS and NMOS devices separately. A NMOS fabrication method includes using tensile films to improve carrier mobility. A PMOS fabrication method includes using substrate structures that apply a compression stress to the channel. One PMOS method includes selective application of a SiGe layer within the source/drain regions. Another method uses modified shallow trench isolation (STI) structures that compress the PMOS channel.
A problem with the prior art is that widely different materials and methods are used for NMOS and PMOS devices. For NMOS devices, a silicon nitride tensile film formed over an essentially completed transistor may be used to improve carrier mobility. For PMOS devices, on the other hand, an embedded SiGe stressor may be formed at a more intermediate fabrication stage. A problem with this approach, however, is that using different materials at different stages of the fabrication process further complicates an already complex process. Therefore, there remains a need for improving the carrier mobility of both NMOS and PMOS devices without significantly adding to the cost or complexity of the manufacturing process.